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JCET (长电科技), a leading Chinese provider of IC back end manufacturing and technology services, announced that it has achieved high-volume integrated packaging for 4-nanometer chips, reported China Daily on January 11.
JCET said it has leveraged chiplet technologies to achieve production of packaging for 4 nm chips for foreign customers, with a maximum packaging area of some 1,500 square millimeters.
This marks a breakthrough in China's chip packaging industry, experts said.
Wu Jiangxing, an academician at the Chinese Academy of Engineering, said chip manufacturing is evolving to embrace more difficult designs and complicated processing. This in turn is causing costs to continue to rise.
Against such a backdrop, chiplets are rising in importance as they can improve productivity and yields, lower design complexity and help cut costs of both design and manufacturing, experts said.
Chiplet is essentially a technology that allows an integrated circuit block to be interconnected with other ICs to form a larger, more complex chip.
With the rapid development of high-performance computing, AI, 5G, smart automobiles, cloud and other applications in recent years, continuous innovation of back-end manufacturing technologies is required to compensate for the slowdown of Moore's Law, JCET said on its official website.
In response to market demand, JCET is working hard to explore new, advanced chip packaging technologies, the company said.
Founded in 1972 and listed on Shanghai Stock Exchange in 2003, JCET is based in Jiangyin，eastern China's Jiangsu Province. Its comprehensive portfolio covers a wide spectrum of semiconductor applications such as smartphones, communications, computing and automobile, through advanced wafer-level packaging.
JCET has two research and development centers in China and South Korea, six manufacturing locations in China, South Korea and Singapore, and sales centers around the world, said the China Daily report.
(HX Chen)
