Synopsys Showcases DesignWare IP Solutions for SuperSpeed USB 3…

作者：蓝天 2010-01-30

来源：prnewswire #USB# #DesignWare# #SuperSpeed# #Showcases# #Solutions#

SANTA CLARA, Calif., Jan. 28 /PRNewswire-FirstCall/ -- Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, will be demonstrating its DesignWare® IP solutions for SuperSpeed USB 3.0, DDR and PCI Express® 3.0 at DesignCon 2010 in Santa Clara, California on February 2-3, 2010.

DesignCon® is the definitive event for electronic design experts spanning chip, package, board, and system domains, addressing common issues in signal integrity, power management, interconnection, and design verification.

WHAT: Synopsys will be showcasing its latest developments in the DesignWare SuperSpeed USB 3.0 and DDR IP in Synopsys Booth #216. The DesignWare IP for PCI Express 3.0 will be shown in the LeCroy Booth #109. In addition, Synopsys will be participating in a number of presentations, tutorials and panels at the show.

WHEN: February 2-3, 2010

WHERE: Santa Clara Convention, 5001 Great America Pkwy., Santa Clara, CA 95054

EXHIBIT HOURS:

Tuesday, February 2	12:30pm - 6:30pm
Wednesday, February 3	12:30pm - 6:30pm

Synopsys Highlights at DesignCon:

DesignWare IP Booth #216

Synopsys Demonstrates SuperSpeed USB 3.0 Interoperability
This demonstration shows proven interoperability of Synopsys' DesignWare USB 3.0 PHY with the DesignWare USB 3.0 host and device controllers implemented in FPGAs. View a high-definition video running at hundreds of megabytes per second.
Synopsys DDR3 Memory Controller Test Chips Operating at 1600 Mbps
Witness full-speed write and read data eyes up to 1600 Mbps, automatic process, voltage and temperature (PVT) drift compensation, internal data eye width measurements, clock jitter measurements and the capabilities within the DDR IP.

LeCroy Booth #109

Bridging the Gap between simulation and hardware debug using DesignWare PCI Express Verification IP and LeCroy's SimPASS PE

The demo will utilize the LeCroy's SimPASS PE protocol application to display and analyze the PCI Express 3.0 traffic generated by the DesignWare PCI Express Verification IP when verifying a design. See how SimPASS enables you to eliminate potential flaws in the data and transaction packets from the I/O stream, allowing developers to more thoroughly test and debug the logic design prior to going into silicon.